The invention is directed to a circuit arrangement for regulating the load current of a power MOSFET to which a load is connected in series at the source side, and comprising the following features:
a) the drain-source path of a second MOSFET is connected between the gate terminal and the source terminal of the power MOSFET; PA1 b) the gate terminal of a third MOSFET is connected to the gate terminal of the power MOSFET; PA1 c) the drain terminals of the third MOSFET and the power MOSFET are connected to one another. PA1 d) the drain-source path of a fourth power MOSFET is connected between the source terminals of the third MOSFET and of the power MOSFET; PA1 e) the gate terminal of the second MOSFET is connected to the junction between third and fourth MOSFETS; and PA1 f) all MOSFETs are enhancement FETs.
Such a circuit arrangement has been disclosed, for example, by EP 0 369 048. It is shown in FIG. 3. The circuit arrangement of the prior art contains a power MOSFET 1 at a source side of which a load 2 is connected in series. The series circuit lies at two output terminals 3,4 that are connected to a supply voltage V.sub.BB. The drain-source path of a second MOSFET 5 lies between the gate terminal G and the source terminal S of MOSFET 1. The series circuit of MOSFET 1 and load 2 has another series circuit composed of a third MOSFET 6 and a current source 7 connected parallel to it. The drain terminal of 6 is connected to the drain terminal of 1. The junction between MOSFET 6 and current source 7 is connected to the gate terminal G of the second MOSFET. The other terminal of the current source is connected to the output terminal 4 that lies at fixed potential, for example ground potential. The gate terminals G of the MOSFETs 6 and 1 are connected to an input terminal 8. The other input terminal is referenced 9 and lies at the same potential as 4, for example ground potential.
The power MOSFET 1 begins to conduct when an input voltage U.sub.IN is applied to the input terminals 8,9 insofar as its cut-off voltage is exceeded. The gate terminal of the MOSFET 5 lies at ground potential vie the current source 7. The power MOSFET 1 continues to be driven more conductive with increasing input voltage, whereby the source potential thereof follows the gate potential. The gate potential of the MOSFET 5 (voltage U7) via the current source 7 likewise follows the input voltage and is lower than the latter by the cut-off voltage U.sub.t6 of the MOSFET 6. When the input voltage reaches a value that is greater than the sum of the supply voltage V.sub.BB and the cut-off voltage U.sub.t6, the MOSFET 6 is fully activated and the potential V.sub.BB is present at the gate of MOSFET 5.
During nominal operation, a predetermined voltage U.sub.DS drops off at the power MOSFET 1. In case of an overload or of a short of the load 2, the transistor current I1 and, thus, the voltage U.sub.DS, rise. When this voltage becomes higher than the cut-off voltage U.sub.t5 of the MOSFET 5, then the latter begins to conduct. The control voltage U.sub.GS of MOSFET 1 is then reduced until the voltage U.sub.GS corresponds to a reduction of the transistor current I1. The height of the control voltage U.sub.GS is limited to the height of the sum of the cut-off voltages U.sub.t5 +U.sub.t6. The circuit arrangement employs a power source that is composed of a depletion MOSFET whose gate terminal is connected to the source terminal. Such a depletion FET, however, is more complicated compared to an enhancement FET and cannot be as precisely manufactured. The precision of the over-current limitation therefore leaves something to be desired.